The present invention relates to a vertical transistor and a method for manufacturing the same, and more particularly, to a vertical transistor in which integration is improved and leakage current is greatly reduced.
Along with the increased integration of semiconductor devices, for example, 1 Gbit DRAMs and beyond, new techniques for manufacturing extremely small transistor elements must be developed. One method of increasing integration is to form a three-dimensional transistor structure, instead of the commonly used planar-type transistor. A three-dimensionally structured transistor having a cylindrical gate electrode has been proposed by H. Takato et al. in a paper entitled "Impact of Surrounding Gate Transistor (SGT) for Ultra-high Density LSI's" (IEEE Transactions on Electron Devices, March 1991, pp.573-577).
FIG. 1 is a section view of the above three-dimensionally structured transistor. Here, reference numeral 10 denotes a semiconductor substrate, reference numeral 12 denotes a first-conduction-type well having convex and concave areas formed by a trench region, reference numeral 14 denotes a gate insulation layer formed in well 12, reference numeral 16 denotes a polysilicon gate electrode on the surface of gate insulation layer 14 formed on the inner sidewalls of well 12, reference numeral 18a denotes a source region of a second conduction type which is different from the first conduction type, reference numeral 18b denotes a second-conduction-type drain region, reference numeral 20 denotes an insulation layer having a contact hole on source region 18a and drain region 18b, and reference numerals 22a and 22b denote a source electrode and a drain electrode connected to source region 18a and drain region 18b, respectively.
According to the above structure, in order to form a channel region between the source and drain of the transistor, a deep trench is formed in a well. Here, the side and bottom surfaces of the trench are damaged during its formation, and the damage has significant adverse effects on the subsequently formed gate insulation layer, channel region and source/drain region, thus causing leakage current. Further, if the transistor of FIG. 1 is employed as an access transistor of a DRAM cell, the process margin for forming a contact hole to connect the source region and the storage electrode is very small. Moreover, a bit-line and bit-line contact are necessarily formed on the drain, which complicates the manufacturing process.